1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Art
Advancement of performance of semiconductor devices has been driven mainly by shrinkage of element. One of effects ascribable to the shrinkage relates to increase in operational speed of active element, by virtue of shortened gate length. Another effect relates to decrease in occupied area of the semiconductor devices, as a result of shortened gate length and reduced interconnect pitch. As one example making use of increased degree of integration of the semiconductor devices, those having a memory circuit and a logic circuit, which had respectively been formed on separate semiconductor substrates, mounted together on the same semiconductor substrate have already been put into practical use.
Performance-related effect of integration of the memory circuit for storing information and the logic circuit for processing the information on the same semiconductor substrate may be understood as that the memory circuit and the logic circuit, having been formed separately in previous days, may be placed closely adjacent to each other in the semiconductor device. Accordingly, connection between the memory circuit and the logic circuit, having been established on a substrate having the semiconductor device mounted thereon, may be enabled inside the semiconductor device. As a consequence, operational speed as an information processing system having a storage device and a logic operation device may be improved. In addition, since the memory circuit and the logic circuit, having previously been formed on separate semiconductor substrates, may be obtained from the same semiconductor substrate, the semiconductor device having the memory circuit and the logic circuit integrated therein, may be manufactured at low cost with good yield.
Manufacturing of the semiconductor device having the memory circuit and the logic circuit integrated therein, however, needs formation of active elements and interconnects for configuring the logic circuit, and additionally needs formation of memory elements necessary for configuring the memory circuit. It has been necessary to adopt a more specialized structure in order to form the memory elements, as compared with the case where the logic circuit is configured.
For an exemplary case where capacitor elements, generally called “trench-type capacitors” are formed on the semiconductor substrate, trenches of as deep as several micrometers or more are formed in the semiconductor substrate. According to the method, since diameters of the trenches to be formed in the semiconductor substrate will necessarily be reduced as the semiconductor elements keep on shrinking, so that the trenches are necessarily deepened if they are concomitantly desired to ensure a sufficient level of capacitance. This means increase in aspect ratio of the trenches formed in the semiconductor substrate. For this reason, it has been very difficult to fill up such high-aspect-ratio trenches with the electrode which composes the capacitor elements.
In order to solve the problem of such high aspect ratio, there has been proposed a capacitor element structure called stacked-type capacitor. Known stacked capacitor element structures include those having fin-type or cylinder-type capacitor elements formed on the semiconductor substrate, so as to configure the memory elements.
For example, Japanese Laid-Open Patent Publication Nos. 2005-005337, 2005-086150, 2002-261256 and H11-026716 disclose structures having cylinder-type capacitor elements formed between active elements formed on the semiconductor substrate and a multi-layered interconnect.
Japanese Laid-Open Patent Publication No. 2003-332463 discloses a structure having parallel plate-type capacitor elements formed over the active elements formed on the semiconductor substrate.
Japanese Laid-Open Patent Publication Nos. 2007-201101, 2000-332216, 2004-342787 and 2005-101647 disclose structures having cylinder-type capacitor elements formed in a stacked insulating film structure which composes a multi-layered interconnect structure formed over the semiconductor substrates.